Related resources
Search for item elsewhere
University researcher(s)
Academic department(s)
Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA
Mahdi Jelodari Mamaghani, Jim D. Garside, Will B. Toms, Doug Edwards
In: Euromicro Conference on Digital System Design (DSD); 27 Aug 2014-29 Aug 2014; Verona, Italy. DOI 10.1109; 2014.
Access to files
-
FULL-TEXT.PDF (pdf)
Abstract
A ‘natural’ way of describing an algorithm is as a data flow. When synthesizing hardware a lot of design effort can be expended on details of mapping this into clock cycles. However there are several good reasons – not least the maturity of Electronic Design Automation (EDA) tools – for implementing circuits synchronously. This paper describes: a) an approach to transform an asynchronous dataflow network into a synchronous elastic implementation whilst retaining the characteristic, relatively free, flow of data. b) work to translate a synchronous elastic dataflow into a synchronous circuit whose deterministic properties pave the road for further behavioural analysis of the system. The results exhibit considerable benefit in terms of area over an asynchronous dataflow realisation.