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Prof Stephen Furber (CBE FRS FREng FBCS FIET CITP CEng) - publications

 

List of publications

Journal article

  • Grymel, M.; Furber, S. B A Novel Programmable Parallel CRC Circuit. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2011 October; 19(10): 1898-1902. eScholarID:103388 | DOI:10.1109/TVLSI.2010.2058872
  • Alexander D Rast M, Furber S. Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System. International Journal of Parallel Programming. 2011 July; 39: eScholarID:155431 | DOI:10.1007/s10766-011-0180-7
  • Alexander Rast S. Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware. Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware, Neural Networks. 2011 November; 24(9): eScholarID:155430 | DOI:10.1016/j.neunet.2011.06.014
  • MM Khan S. Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric. Parallel Computing Volume 37. 2011 August; 37(8): eScholarID:155417 | DOI:10.1016/j.parco.2011.02.003
  • Bhattacharya, B.S.; Furber, S.B Biologically Inspired Means for Rank-Order Encoding Images: A Quantitative Analysis. Neural Networks, IEEE Transactions on. 2010 July; 21(7): 1087-1099. eScholarID:103386 | DOI:10.1109/TNN.2010.2048339
  • Xin Jin; Lujan, M.; Plana, L.A.; Davies, S.; Temple, S.; Furber, S.B Modeling Spiking Neural Networks on SpiNNaker. Computing in Science & Engineering. 2010 September; 12(5): 91-98. eScholarID:103393 | DOI:10.1109/MCSE.2010.112
  • Jian Wu; Steve Furber. A Multicast Routing Scheme for a Universal Spiking Neural Network Architecture. The Computer Journal, Vol. 53 No. 3, 2010. 2009 April; 53(3): 280-288. eScholarID:103079 | DOI:10.1093/comjnl/bxp024
  • Furber S. The Future of Computer Technology and its Implications for the Computer Industry. Comput. J. 2008; 51(6): 735-740. eScholarID:1h202 | DOI:10.1093/comjnl/bxn022
  • Furber S, Temple S. Neural systems engineering. Journal of the Royal Society Interface. 2007 April; 4(13): 193-206. eScholarID:1f696 | DOI:10.1098/rsif.2006.0177
  • Furber S, Brown G, Bose J, Cumpstey J, Marshall P, Shapiro J. Sparse Distributed Memory Using Rank-Order Neural Codes. IEEE Transactions on Neural Networks. 2007; 18(3): 648-659. eScholarID:1h204
  • Plana L, Furber S, Temple S, Khan M, Shi Y, Wu J, Yang S. A GALS Infrastructure for a Massively Parallel Multiprocessor. IEEE Design & Test of Computers. 2007; 24(5): 454-463. eScholarID:1h203
  • Bose J, Furber S, Shapiro J. An associative memory for the on-line recognition and prediction of temporal sequences. CoRR. 2006; abs/cs/0611020: eScholarID:1h515
  • S. B. Furber, W. J. Bainbridge, J. M. Cumpstey and S. Temple. A Sparse Distributed Memory based upon N-of-M Codes. Neural Networks. 2004; 17: eScholarID:1a5297
  • FURBER SB; YAKOVLEV A; KRENZ R; BYSTROV A. Design and Analysis of a Self-Timed Duplex Communication System. IEEE Transactions on Computers. 2004 July; 53(7): 798-814. eScholarID:1a10206 | DOI:10.1109/TC.2004.26
  • FURBER SB; TEMPLE S; CUMPSTEY M; BAINBRIDGE J. Sparse distributed memory using N-of-M codes. Neural Networks. 2004 October; 17(10): 1437-1451. eScholarID:1a10209 | DOI:10.1016/j.neunet.2004.07.003
  • Furber S, Bainbridge J, Cumpstey J, Temple S. Sparse distributed memory using N-of-M codes. Neural Networks. 2004; 17(10): 1437-1451. eScholarID:1h207 | DOI:10.1016/j.neunet.2004.07.003
  • Felicijan T, Furber S. An asynchronous ternary logic signaling system. IEEE Trans. VLSI Syst. 2003; 11(6): 1114-1119. eScholarID:1h208
  • Furber S. Editorial. Microprocessors and Microsystems. 2003; 27(9): 407-408. eScholarID:1h210 | DOI:10.1016/S0141-9331(03)00090-5
  • Hormdee D, Garside J, Furber S. An asynchronous copy-back cache architecture. Microprocessors and Microsystems. 2003; 27(10): 485-500. eScholarID:1h209 | DOI:10.1016/S0141-9331(03)00101-7
  • Bainbridge J, Furber S. Chain: A Delay-Insensitive Chip Area Interconnect. IEEE Micro. 2002; 22(5): 16-23. eScholarID:1h212
  • Furber S. Validating the AMULET Microprocessors. Comput. J. 2002; 45(1): 19-26. eScholarID:1h211
  • Furber S, Efthymiou A, Garside J, Lloyd D, Lewis M, Temple S. Power Management in the Amulet Microprocessors. IEEE Design & Test of Computers. 2001; 18(2): 42-52. eScholarID:1h222
  • Woods J, Day P, Furber S, Garside J, Paver N, Temple S. AMULET1: A Asynchronous ARM Microprocessor. IEEE Trans. Computers. 1997; 46(4): 385-398. eScholarID:1h223
  • Furber S, Day P. Four-phase micropipeline latch control circuits. IEEE Trans. VLSI Syst. 1996; 4(2): 247-253. eScholarID:1h215

Conference contribution

  • Sergio Davies, Alexander Rast, Francesco Galluppi and Steve Furber. A forecast-based biologically-plausible STDP learning rule. Proc. 2011 International Joint Conference on Neural Networks (IJCNN). USA: IEEE: 2011: 1810-1817. eScholarID:138691 | DOI:10.1109/IJCNN.2011.6033444
  • Alexander Rast, Francesco Galluppi, Sergio Davies, Luis A. Plana, Thomas Sharp and Steve Furber. An event-driven model for the SpiNNaker virtual synaptic channel. Neural Networks (IJCNN), The 2011 International Joint Conference on. USA: IEEE: 2011: 1967-1974. eScholarID:138689 | DOI:10.1109/IJCNN.2011.6033466
  • Sharp, T. ; Patterson, C. ; Furber, S. Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware. Proc. Neural Networks (IJCNN), The 2011 International Joint Conference on. USA: IEEE: 2011: 1099-1105. eScholarID:138695 | DOI:10.1109/IJCNN.2011.6033346
  • Thomas Sharp, Luis A. Plana, Francesco Galluppi and Steve Furber. Event-Driven Simulation of Arbitrary Spiking Neural Networks on SpiNNaker. Lecture Notes in Computer Science, Volume: 7064. Berlin / Heidelberg: Springer: 2011: 424-430. eScholarID:138654 | DOI:10.1007/978-3-642-24965-5_48
  • Sergio Davies, Alexander Rast, Francesco Galluppi, Steve B. Furber. Maintaining real-time synchrony on SpiNNaker. Proc. of the 8th ACM International Conference on Computing Frontiers. New York, USA.: ACM: 2011: 15:1-15:2. eScholarID:138701 | DOI:10.1145/2016604.2016622
  • Merrett, M.; Asenov, P.; Yangang Wang; Zwolinski, M.; Reid, D.; Millar, C.; Roy, S.; Zhenyu Liu; Furber, S.; Asenov, A. Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011. USA: IEEE: 2011: 1-4. eScholarID:138918
  • Galluppi, F. ; Furber, S. Representing and decoding rank order codes using polychronization in a network of spiking neurons. Proc. he 2011 International Joint Conference on Neural Networks (IJCNN). USA: IEEE: 2011: 943-950. eScholarID:138698 | DOI:10.1109/IJCNN.2011.6033324
  • Javier Navaridas, Luis A. Plana, Jose Miguel-Alonso, Mikel Luján, Steve B. Furber. SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network. CF '10 Proceedings of the 7th ACM international conference on Computing frontiers. New York, USA: ACM: 2010: 11-19. eScholarID:103249 | DOI:10.1145/1787275.1787278
  • Sergio Davies, Cameron Patterson, Francesco Galluppi, Alexander D. Rast, David Lester, and Steve B. Furber. Interfacing Real-Time Spiking I/O with the SpiNNaker neuromimetic architecture. Proceedings 17th International Conference, ICONIP 2010. Australia: Australian Journal of Intelligent Information Processing Systems, Vol.11, No. 1,: 2010: 7-11. eScholarID:103411
  • Alexander D. Rast, Xin Jin, Francesco Galluppi, Luis A. Plana, Cameron Patterson, Steve Furber. Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system. Proceedings CF '10 Proceedings of the 7th ACM international conference on Computing frontiers. New York, USA: ACM: 2010: 21-29. eScholarID:103242 | DOI:10.1145/1787275.1787279
  • Francesco Galluppi, Alexander Rast, Sergio Davies and Steve Furber. A General-Purpose Model Translation System for a Universal Neural Chip. Neural Information Processing. Theory and Algorithms 17th International Conference, ICONIP 2010. Berlin / Heidelberg: Springer: 2010: 58-65. eScholarID:109003 | DOI:10.1007/978-3-642-17537-4_8
  • Andrew Brown, Steve Furber, Jeff Reeve, Peter Wilson, Mark Zwolinski, John Chad, Luis Plana, David Lester. A communication infrastructure for a million processor machine. Proceedings of the 7th ACM international conference on Computing frontiers. New York, USA: ACM: 2010: 75-76. eScholarID:103224 | DOI:10.1145/1787275.1787290
  • Xin Jin ; Galluppi, F. ; Patterson, C. ; Rast, A. ; Davies, S. ; Temple, S. ; Furber, S. . Algorithm and software for simulation of spiking neural networks on the multi-chip SpiNNaker system. The 2010 International Joint Conference on Neural Networks (IJCNN). USA: IEEE: 2010: 649-656. eScholarID:103376 | DOI:10.1109/IJCNN.2010.5596759
  • Browse > Conferences> Parallel and Distributed Compu ... PDF - Access Full Text Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware * 5532476 abstract Download Citations * Email * Print * Rights And Permissions * Jin, X.; Luján, M.; Khan, M.M.; Plana, L.A.; Rast, A.D.; Welbourne, S.R.; Furber, S.B. Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware. Proc. Ninth International Symposium on Parallel and Distributed Computing (ISPDC), 2010. USA: IEEE: 2010: 9-16. eScholarID:103257 | DOI:10.1109/ISPDC.2010.10
  • Xin Jin, Mikel Luján, Luis A. Plana, Alexander D. Rast, Stephen R. Welbourne, Steve B. Furber. Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker. CF '10 Proceedings of the 7th ACM international conference on Computing frontiers. New York, USA: ACM: 2010: 88-90. eScholarID:103237 | DOI:10.1145/1787275.1787297
  • Xin Jin ; Rast, A. ; Galluppi, F. ; Davies, S. ; Furber, S. . Implementing spike-timing-dependent plasticity on SpiNNaker neuromorphic hardware. Proc. 2010 International Joint Conference on Neural Network (IJCNN)s. USA: IEEE: 2010: 2302-2309. eScholarID:103296 | DOI:10.1109/IJCNN.2010.5596372
  • Humble, J., Furber, S.; Denham, S. and Wennekers, T. STDP pattern onset learning depends on background activity. Proceedings of BICS 2010 - Brain Inspired Cognitive Systems 14-16 July 2010, Madrid, Spain. 2010: -. eScholarID:103412
  • Rast, A.D. ; Galluppi, F. ; Jin, X. ; Furber, S.B. . The Leaky Integrate-and-Fire neuron: A platform for synaptic model exploration on the SpiNNaker chip. Neural Networks (IJCNN), The 2010 International Joint Conference on. USA: IEEE: 2010: 3959-3966. eScholarID:103292 | DOI:10.1109/IJCNN.2010.5596364
  • S.B. Furber and A.D. Brown. Biologically-Inspired Massively-Parallel Architectures - computing beyond a million processors. Proc. 2009 9th International Conference on Application of Concurrency to System Design (ACSD 2009). USA: IEEE: 2009: -. eScholarID:103091 | DOI:10.1109/ACSD.2009.17
  • Jian Wu; Furber, S.; Garside, J. A Programmable Adaptive Router for a GALS Parallel System. Proc. IEEE Symposium on Asynchronous Circuits and Systems, 2009. USA: IEEE: 2009: 23-31. eScholarID:102971 | DOI:10.1109/ASYNC.2009.17
  • Shufan Yang, Steve B. Furber, Yebin Shi, Luis A. Plana. A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect. Fundamenta Informaticae Volume 95, Number 1 / 2009. IOS Press: 2009: 53-72. eScholarID:103073 | DOI:10.3233/FI-2009-142
  • Rast, A.D.; Khan, M.M.; Jin, X.; Plana, L.A.; Furber, S.B. A universal abstract-time platform for real-time neural networks. Proc. ICNN 2009. International Joint Conference on Neural networks. USA: IEEE: 2009: 2611-2818. eScholarID:102993 | DOI:10.1109/IJCNN.2009.5179067
  • Shufan Yang ; Furber, S.B. ; Plana, L.A. Adaptive admission control on the SpiNNaker MPSoC. Proc. IEEE International SOC Conference, 2009. SOCC 2009. USA: IEEE: 2009: 243-246. eScholarID:103204 | DOI:10.1109/SOCCON.2009.5398050
  • Sen, B.; Furber, S. Evaluating rank-order code performance using a biologically-derived retinal model. Proc. International Joint Conference onNeural Networks, 2009. USA: IEEE: 2009: 2867-2874. eScholarID:102995 | DOI:10.1109/IJCNN.2009.5178842
  • Khan, M.M.; Navaridas, J.; Rast, A.D.; Jin, X.; Plana, L.A.; Lujan, M.; Woods, J.V.; Miguel-Alonso, J.; Furber, S.B. Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric. Proc. Eighth International Symposium on Parallel and Distributed Computing, 2009. ISPDC '09. USA: IEEE: 2009: 54-61. eScholarID:103001 | DOI:10.1109/ISPDC.2009.25
  • Yebin Shi; Furber, S.B.; Garside, J.; Plana, L.A. Fault Tolerant Delay Insensitive Inter-chip Communication. Proc. IEEE Symposium on Asynchronous Circuits and Systems, ASYNC 2009. USA: IEEE: 2009: 77-84. eScholarID:102981 | DOI:10.1109/ASYNC.2009.21
  • Yebin Shi; Furber, S.B.; Garside, J.; Plana, L.A. Fault Tolerant Delay Insensitive Inter-chip Communication. Proc. IEEE Symposium on Asynchronous Circuits and Systems, 2009. USA: IEEE: 2009: 77-84. eScholarID:102991 | DOI:10.1109/ASYNC.2009.21
  • Rast, A.D.; Welbourne, S.; Jin, X.; Furber, S.B. Optimal connectivity in hardware-targetted MLP networks. Proceedings 2009 International Joint Conference on Neural Networks, IJCNN2009. USA: IEEE: 2009: 2619-2626. eScholarID:102996 | DOI:10.1109/IJCNN.2009.5178831
  • Garside, J.D. ; Furber, S.B. ; Temple, S. ; Woods, J.V. . The Amulet chips: Architectural development for asynchronous microprocessors. Proc. 16th IEEE International Conference on Electronics, Circuits, and Systems, 2009. ICECS 2009. USA: IEEE: 2009: 343-343. eScholarID:103214 | DOI: 10.1109/ICECS.2009.5411006
  • Brown, Andrew D, David R Lester, Luis A Plana, Steve Furber, and Peter R Wilson. SpiNNaker: The Design Automation Problem. ICONIP (2). Springer: 2009: 1049-1056. eScholarID:2h382 | DOI:10.1007/978-3-642-03040-6_127
  • Navaridas, Javier, Mikel Luján, José Miguel-Alonso, Luis A Plana, and Steve Furber. Understanding the interconnection network of SpiNNaker. ICS. ACM: 2009: 286-295. eScholarID:2h384
  • Rast, Alexander D, Xin Jin, Mukaram Khan, and Steve Furber. The Deferred Event Model for Hardware-Oriented Spiking Neural Networks. ICONIP (2). Springer: 2009: 1057-1064. eScholarID:2h383 | DOI:10.1007/978-3-642-03040-6_128
  • Jin, Xin, Stephen B Furber, and John V Woods. Efficient modelling of spiking neural networks on a scalable chip multiprocessor. IJCNN. IEEE: 2008: 2812-2819. eScholarID:2h387 | DOI:10.1109/IJCNN.2008.4634194
  • Khan, M M, D R Lester, L A Plana, A Rast, X Jin, E Painkras, S B Furber, and Ieee Ieee. SpiNNaker: Mapping Neural Networks onto a Massively-Parallel Chip Multiprocessor. International Joint Conference on Neural Networks. Ieee: 2008: 2849-2856. eScholarID:2f58
  • Plana, Luis A, John Bainbridge, Steve Furber, Sean Salisbury, Yebin Shi, and Jian Wu. An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. NOCS. IEEE Computer Society: 2008: 215-216. eScholarID:2h389
  • Rast, Alexander D, Shufan Yang, Mukaram Khan, and Stephen B Furber. Virtual synaptic interconnect using an asynchronous network-on-chip. IJCNN. IEEE: 2008: 2727-2734. eScholarID:2h386 | DOI:10.1109/IJCNN.2008.4634181
  • Yang, Shufan, Steve Furber, Yebin Shi, and Luis A Plana. An admission control system for QoS provision on a best-effort GALS interconnect. ACSD. IEEE: 2008: 200-207. eScholarID:2h385 | DOI:10.1109/ACSD.2008.4574612
  • Ebergen, Jo C, Steve Furber, and Arash Saifhashemi. Notes On Pulse Signaling. ASYNC. IEEE Computer Society: 2007: 15-24. eScholarID:2h390
  • Sen, B, and S Furber. Maximising information recovery from rank-order codes - art. no. 65700C. Conference on Data Mining, Intrusion Detection, Information Assurance and Data Networks Security 2007. Spie-Int Soc Optical Engineering: 2007: C5700-C5700. eScholarID:2f112
  • Furber, Stephen B, Steve Temple, and Andrew D Brown. On-chip and inter-chip networks for modeling large-scale neural systems. ISCAS. IEEE: 2006: eScholarID:2h392 | DOI:10.1109/ISCAS.2006.1692992
  • Furber, Steve. Living with Failure: Lessons from Nature?. European Test Symposium. IEEE Computer Society: 2006: 4-8. eScholarID:2h391
  • Liu, Yijun, Steve Furber, and Zhenkun Li. The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing. PATMOS. Springer: 2006: 425-438. eScholarID:2h393 | DOI:10.1007/11847083_41
  • Bose, Joy, Stephen B Furber, and Jonathan L Shapiro. A Spiking Neural Sparse Distributed Memory Implementation for Learning and Predicting Temporal Sequences. ICANN (1). Springer: 2005: 115-120. eScholarID:2h394 | DOI:10.1007/11550822_19
  • Bose, Joy, Stephen B Furber, and Jonathan L Shapiro. A System for Transmitting a Coherent Burst of Activity Through a Network of Spiking Neurons. WIRN/NAIS. Springer: 2005: 44-48. eScholarID:2h1110 | DOI:10.1007/11731177_7
  • Liu, Yijun, and Stephen B Furber. A Low Power Embedded Dataflow Coprocessor. ISVLSI. IEEE Computer Society: 2005: 246-247. eScholarID:2h395
  • Liu, Yijun, and Stephen B Furber. The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics. PATMOS. Springer: 2005: 647-656. eScholarID:2h396 | DOI:10.1007/11556930_66
  • Bainbridge, W J, Luis A Plana, and Stephen B Furber. The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip. DATE. IEEE Computer Society: 2004: 274-279. eScholarID:2h398
  • Liu, Yijun, and Stephen B Furber. Minimizing the Power Consumption of an Asynchronous Multiplier. PATMOS. Springer: 2004: 289-300. eScholarID:2h400
  • Liu, Yijun, and Stephen B Furber. The design of a low power asynchronous multiplier. ISLPED. ACM: 2004: 301-306. eScholarID:2h399
  • Bainbridge, W J, W B Toms, David A Edwards, and Stephen B Furber. Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes. ASYNC. IEEE Computer Society: 2003: 132-140. eScholarID:2h401
  • Yu, Z C, Stephen B Furber, and Luis A Plana. An Investigation into the Security of Self-Timed Circuits. ASYNC. IEEE Computer Society: 2003: 206-215. eScholarID:2h402
  • Hormdee, Daranee, Jim D Garside, and Stephen B Furber. An Asynchronous Victim Cache. DSD. IEEE Computer Society: 2002: 4-11. eScholarID:2h435
  • Bainbridge, W J, and Stephen B Furber. Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding. ASYNC. IEEE Computer Society: 2001: 118-126. eScholarID:2h404
  • Riocreux, P A, L E M Brackenbury, J Mike Cumpstey, and Stephen B Furber. A Low-Power Self-Timed Viterbi Decoder. ASYNC. IEEE Computer Society: 2001: 15-24. eScholarID:2h405
  • Furber, Stephen B, David A Edwards, and Jim D Garside. AMULET3: A 100 MIPS Asynchronous Embedded Processor. ICCD. 2000: 329-334. eScholarID:2h442
  • Garside, Jim D, W J Bainbridge, Andrew Bardsley, David M Clark, David A Edwards, Stephen B Furber, David W Lloyd, S Mohammadi, J S Pepper, Steve Temple, J V Woods, Jianwei Liu, and O Petli. AMULET3i - An Asynchronous System-on-Chip. ASYNC. IEEE Computer Society: 2000: 162-175. eScholarID:2h441
  • Garside, Jim D, Stephen B Furber, and S-H Chung. AMULET3 Revealed. ASYNC. IEEE Computer Society: 1999: 51-59. eScholarID:2h444
  • Bainbridge, W J, and Stephen B Furber. Asynchronous Macrocell Interconnect using MARBLE. ASYNC. IEEE Computer Society: 1998: 122-132. eScholarID:2h409
  • Endecott, Philip, and Stephen B Furber. Modelling and Simulation of Asynchronous Systems Using the LARD Hardware Description Language. ESM. SCS Europe: 1998: 39-43. eScholarID:2h411
  • Tan, Sun-Yen, Stephen B Furber, and Wen-Fang Yen. The Design of an Asynchronous VHDL Synthesizer. DATE. IEEE Computer Society: 1998: 44-51. eScholarID:2h410
  • Furber, Stephen B, Jim D Garside, Steve Temple, Jianwei Liu, P Day, and N C Paver. AMULET2e: An Asynchronous Embedded Controller. ASYNC. IEEE Computer Society: 1997: 290-. eScholarID:2h447
  • Petlin, O A, and Stephen B Furber. Built-In Self-Testing of Micropipelines. ASYNC. IEEE Computer Society: 1997: 22-29. eScholarID:2h412
  • Furber, Stephen B. The Return of Asynchronous Logic. ITC. IEEE Computer Society: 1996: 938. eScholarID:2h414
  • Petlin, O A, and Stephen B Furber. Scan testing of asynchronous sequential circuits. Great Lakes Symposium on VLSI. IEEE Computer Society: 1995: 224-229. eScholarID:2h415
  • Petlin, O A, and Stephen B Furber. Scan testing of micropipelines. VTS. IEEE Computer Society: 1995: 296-303. eScholarID:2h416
  • Furber, Stephen B, P Day, Jim D Garside, N C Paver, and J V Woods. AMULET1: A Micropipelined ARM. COMPCON. 1994: 476-485. eScholarID:2h448
  • Furber, Stephen B, P Day, Jim D Garside, N C Paver, Steve Temple, and J V Woods. The Design and Evaluation of an Asynchronous Microprocessor. ICCD. IEEE Computer Society: 1994: 217-220. eScholarID:2h449
  • Furber, Stephen B, P Day, Jim D Garside, N C Paver, and J V Woods. A micropipelined ARM. VLSI. North-Holland: 1993: 211-220. eScholarID:2h451
  • Paver, N C, P Day, Stephen B Furber, Jim D Garside, and J V Woods. Register Locking in an Asynchronous Microprocessor. ICCD. IEEE Computer Society: 1992: 351-355. eScholarID:2h452

Conference proceeding

  • Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993. 1993. eScholarID:6h73

Book contribution

  • Furber S, Temple S. Neural Systems Engineering. Computational Intelligence: A Compendium. Springer.2008: eScholarID:3h7 | DOI:10.1007/978-3-540-78293-3_18

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