My research is in the area of computer engineering. I lead the Advanced Processor Technologies research group within the School of Computer Science. My current particular interests are detailed below.
The classical computational paradigm performs impressive feats of calculation but fails in some of the simplest tasks that we humans undertake with ease and from a very early age. Biological neural networks are proof that there are alternative computational architectures that can outperform our fastest systems in tasks such as face recognition, speech processing, and the use of natural language. Brains are complex highly-parallel systems that employ imperfect and slow (though exceedingly power-efficient) components in asynchronous dynamical configurations to carry out sophisticated information processing functions. Note the word asynchronous in the previous sentence! Many aspects of brain function are little-understood, but we hope that our deep understanding of the engineering of complex asynchronous systems may be of use in the Grand Challenge of understanding the architecture of brain and mind. At present our major activity here is the SpiNNaker project, where we are building a massively-parallel chip multiprocessor system for modelling large systems of spiking neurons in real time.
You can find a simple simulation of the effects of evolution on the performance of a simple neural network here.
As Systems-on-Chip become ever more complex the problem of linking together the various modules that make up the complete system - the processor, memory, peripherals, signal processing hardware, and so on - becomes ever more complex. The solution for simpler SoCs was to use buses, but already high-end SoCs require hierarchies of buses to meet their performance targets. Ultimately this will lead to on-chip interconnect that is better viewed as a network rather than as a bus. Networks-on-Chip are at their most flexible if they are self-timed, and a GALS - Globally Asynchronous Locally Synchronous - architecture emerges that allows each module to operate with its own independent clock (or, for the more adventurous, no clock at all!). Our past work focussed on the GALS network fabric (e.g. CHAIN) and on Quality-of-Service issues. Most of this activity has now moved out into Silistix Ltd, although there is a lot of NoC work (including use of Silistix tools) within the SpiNNaker project described above.
Since 1990 I have been building large-scale asynchronous VLSI systems, most notably the Amulet processor series detailed elsewhere on these web pages.
Personal details | Research | Publications | Teaching
This website will look much better in a web browser that supports web standards, but it is accessible to any browser or Internet device.