MEng Software Engineering

Year of entry: 2020

Course unit details:
Chip Multiprocessors

Unit code COMP35112
Credit rating 10
Unit level Level 3
Teaching period(s) Semester 2
Offered by Department of Computer Science
Available as a free choice unit? No

Overview

Due to technological limitations, it is proving increasingly difficult to maintain a continual increase in the performance of individual processors. Therefore, the current trend is to integrate multiple processors on to a single chip and exploit the resulting parallel resources to achieve higher computing power. However, this may require significantly different approaches to both hardware and software particularly for general purpose applications. This course will explore these issues in detail.

Pre/co-requisites

Unit title Unit code Requirement type Description
System Architecture COMP25212 Pre-Requisite Compulsory
Students who are not from the School of Computer Science must have permission from both Computer Science and their home School to enrol.

Learning outcomes

  • describe the main issues, along with key proposed solutions, in the design and construction of chip multi-processor hardware (e.g. multi-core CPUs and GPUs) and related programming languages.

  • evaluate a number of specific examples of extensions to programming languages supporting the writing of correct and efficient code on shared memory multi-processors.

  • compare a number of extensions to hardware structures supporting, for example, memory coherence, synchronization, speculation and transactional memory, to improve the performance of code executing on chip multiprocessors.

  • compare a number of extensions to programming languages and supporting data structures, including so-called "lock-free" data structures, to improve the performance of code on chip multiprocessors.

  • evaluate the effectiveness of concurrency support in Java, including the use of threads, locks and barriers, in the context of experience gained with three simple parallel programming exercises.

Syllabus

Introduction

Trends in technology, limitations and consequences. The move to multi-coreParallelism in programs, ILP, Thread Level, Data Parallelism.

Parallel Architectures

SIMD, MIMD, Shared Memory, Distributed Memory, strengths and weaknesses.

Parallel Programming

Multithreaded programming, Data parallel programming, Explicit vs Implicit parallelism, automatic parallelisation. The Case for Shared Memory. When to share?

Shared Memory Multiprocessors

Basic structures, the cache coherence problem. The MESI protocol. Limitations. Directory based coherence.

Programming with Locks and Barriers

The need for synchronisation. Problems with explicit synchronisation

Other Parallel Programming Approaches

MPI and OpenMP

Speculation

The easy route to automatic parallelisation?

Transactional Memory

Principles. Hardware and Software approaches

Memory Issues

Memory system design. Memory consistency

Other Architectures and Programming Approaches

GPGPUs, CUDA

Data Driven Parallelism

Dataflow principles and Functional Programing

Employability skills

Analytical skills
Problem solving
Written communication
Other

Assessment methods

Method Weight
Written exam 70%
Written assignment (inc essay) 30%

Feedback methods

Written feedback on reports for laboratory exercises. Students who attempt previous exam questions can get feedback on their answers.

Recommended reading

COMP35112 reading list can be found on the School of Computer Science website for current students.

Study hours

Scheduled activity hours
Lectures 24
Independent study hours
Independent study 76

Teaching staff

Staff member Role
John Gurd Unit coordinator

Additional notes

Course unit materials

Links to course unit teaching materials can be found on the School of Computer Science website for current students.

Return to course details