MEng Electronic Engineering

Year of entry: 2021

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Course unit details:
VLSI Design

Unit code EEEN20053
Credit rating 10
Unit level Level 2
Teaching period(s) Semester 2
Offered by Department of Electrical & Electronic Engineering
Available as a free choice unit? No

Overview

Brief description of the unit:

Static CMOS gates: MOSFET devices, inverter, DC and transient characteristics, logic gates (NAND, NOR, complex gates), transistor sizing.

Performance and Power issues: gate delay, delay models, speed optimisation, power dissipation, static and dynamic power, low-power design techniques,

Wires and Variability: interconnect, impact of wiring parasitic, variability, technology trends.

Physical Design and Verification: EDA tools, layout design, design rules check (DRC), layout versus schematic (LVS), parasitics extraction, simulation, device models and process corners, corner analysis, Monte Carlo methods.

CMOS design: Transmission gates, multiplexers, latches and flip-flops, dynamic logic.

Memory circuits: static RAM, dynamic RAM, Flash.

Pre/co-requisites

Unit title Unit code Requirement type Description
Digital System Design I EEEN10026 Pre-Requisite Compulsory
Digital Systems Design II EEEN20023 Pre-Requisite Compulsory
Electronic Circuit Design II EEEN20025 Co-Requisite Compulsory
Microelectronic Components EEEN20026 Co-Requisite Compulsory

Aims

This course unit detail provides the framework for delivery in 2020/21 and may be subject to change due to any additional Covid-19 impact.  Please see Blackboard / course unit related emails for any further updates.

The course unit aims to:

To introduce students to the design of Very Large Scale Integration (VLSI) microelectronic circuits, focussing on back-end integrated circuit design (custom transistor-level layout as well as design flow based on standard cells) using industry-standard Electronic Design Automation (EDA) tools.

Learning outcomes

All of the following Intended Learning Outcomes are developed and assessed. On the successful completion of the course unit, students will be able to:

 

ILO 1

Describe the structure and operating characteristics of basic CMOS cells (logic gates, latches) and design styles (static CMOS, dynamic CMOS).

ILO 2

Outline the principle of operation of circuits used in memory systems.

ILO 3

Explain the performance limitations of CMOS circuits, variability and future technology trends.

ILO 4

Design digital circuits at the transistor-level and develop the corresponding layout for an IC fabrication process.

ILO 5

Select appropriate digital circuit implementations to meet specified system requirements.

ILO 6

Use industry-standard IC design (EDA) tools to execute the design of a CMOS cell, including transistor-level circuit design, simulation, layout and design verification.

ILO 7

Produce technical reports relating to coursework and practical assignments.

 

Teaching and learning methods

Teaching and learning processes include twenty hours of lectures, four hours of tutorials and four three-hour laboratory sessions (here, students use industry-standard IC design tool in a computer cluster). Additional support provided using assignment help sessions and an online discussion forum.

64 hours of private study expected.

 

 

Assessment methods

Method Weight
Other 40%
Written exam 60%

Written Examination

60% of the total mark

Coursework

40% of the total mark. The coursework mark consists of four laboratory reports (2.5% each) and two design assignments (20% and 10%).

Recommended reading

-          Weste, Neil H. E., and David Money. Harris. Integrated Circuit Design. 4th ed. Boston: Pearson / Addison.

-          Weste, Neil H. E., and David. Harris. CMOS VLSI Design: a Circuits and Systems Perspective. 4th ed. or 3rd ed. Boston: Pearson Addison Wesley.

Weste, Neil H. E., and Kamran Eshraghian. Principles of CMOS VLSI Design: a Systems Perspective. 2nd ed. Reading, Mass.: Addison-Wesley Pub. Co.

Study hours

Scheduled activity hours
Lectures 20
Practical classes & workshops 12
Tutorials 4
Independent study hours
Independent study 64

Teaching staff

Staff member Role
Jayawan Hasanka Bandara Wijekoon Herath Mudiyanselage Unit coordinator

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