- UCAS course code
- UCAS institution code
BEng Electronic Engineering with Industrial Experience
Year of entry: 2023
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Course unit details:
Digital Systems Design II
|Unit level||Level 2|
|Teaching period(s)||Semester 1|
|Offered by||Department of Electrical & Electronic Engineering|
|Available as a free choice unit?||No|
This unit will cover the following:
- Digital system design process. EDA tools and design viewpoints. Behavioural, dataflow, and gate-level descriptions.
- Hardware description languages. VHDL modelling concepts. Behavioural and structural architecture descriptions. Concurrent and sequential statements. Event-driven simulation.
- Building blocks for digital systems: tri-state buffers, multiplexers, latches, flip-flops, registers, counters, arithmetic circuits, finite state machines.
- Design methodology. Synchronous systems. Top down design. Register-transfer-level design. Test benches. Synthesis from VHDL.
- Implementation issues: gate delays, timing, critical path, communication between unsynchronised machines, coping with metastability.
- Introduction to Programmable Logic Devices (FPGAs, CPLDs)
|Unit title||Unit code||Requirement type||Description|
|Digital System Design I||EEEN10131||Pre-Requisite||Compulsory|
This course unit detail provides the framework for delivery in the current academic year and may be subject to change due to any additional Covid-19 impact. Please see Blackboard / course unit related emails for any further updates.
This course unit aims to:
- Enable students to use structured digital system design methods, hardware description languages and verification tools to design digital systems.
- Expose students to practical implementation issues for digital systems.
On the successful completion of the course, students will be able to:
Predict behaviour of a component specified using a Hardware Description Language (VHDL).
Produce VHDL descriptions of digital data-path components, finite state machines and algorithmic state machines.
Design and implement simple synchronous digital systems using FPGA hardware.
Estimate timing performance limits of a given digital circuit.
Teaching and learning methods
Course work forms 20% of the unit assessment and is both formative and summative. Completion of all coursework is mandatory.
|Scheduled activity hours|
|Practical classes & workshops||9|
|Independent study hours|
|Piotr Dudek||Unit coordinator|