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MEng Mechatronic Engineering / Course details

Year of entry: 2024

Course unit details:
Digital Systems Design II

Course unit fact file
Unit code EEEN20121
Credit rating 10
Unit level Level 2
Teaching period(s) Semester 1
Offered by Department of Electrical & Electronic Engineering
Available as a free choice unit? No

Overview

This unit will cover the following:

  • Digital system design process. EDA tools and design viewpoints. Behavioural, dataflow, and gate-level descriptions.
  • Hardware description languages. VHDL modelling concepts. Behavioural and structural architecture descriptions. Concurrent and sequential statements. Event-driven simulation.
  • Building blocks for digital systems: tri-state buffers, multiplexers, latches, flip-flops, registers, counters, arithmetic circuits, finite state machines. 
  • Design methodology. Synchronous systems. Top down design. Register-transfer-level design. Test benches. Synthesis from VHDL. 
  • Implementation issues: gate delays, timing, critical path, communication between unsynchronised machines, coping with metastability.
  • Introduction to Programmable Logic Devices (FPGAs, CPLDs)

Pre/co-requisites

Unit title Unit code Requirement type Description
Digital System Design I EEEN10131 Pre-Requisite Compulsory

Aims

This course unit detail provides the framework for delivery in the current academic year and may be subject to change due to any additional Covid-19 impact.  Please see Blackboard / course unit related emails for any further updates.

This course unit aims to:

  • Enable students to use structured digital system design methods, hardware description languages and verification tools to design digital systems.
  • Expose students to practical implementation issues for digital systems.

Learning outcomes

On the successful completion of the course, students will be able to:

Developed

Assessed

ILO 1

Predict behaviour of a component specified using a Hardware Description Language (VHDL).

X

X

ILO 2

Produce VHDL descriptions of digital data-path components, finite state machines and algorithmic state machines.

X

X

ILO 3

Design and implement simple synchronous digital systems using FPGA hardware.

X

X

ILO 4

Estimate timing performance limits of a given digital circuit.

X

X

 

Teaching and learning methods

 

Assessment methods

Method Weight
Other 20%
Written exam 80%

Coursework:

Course work forms 20% of the unit assessment and is both formative and summative. Completion of all coursework is mandatory.

Study hours

Scheduled activity hours
Lectures 20
Practical classes & workshops 9
Tutorials 4
Independent study hours
Independent study 67

Teaching staff

Staff member Role
Piotr Dudek Unit coordinator

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