- UCAS course code
- H613
- UCAS institution code
- M20
BEng Electronic Engineering with Industrial Experience / Course details
Year of entry: 2024
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Course unit details:
Computer Systems Architecture
Unit code | EEEN30222 |
---|---|
Credit rating | 10 |
Unit level | Level 3 |
Teaching period(s) | Semester 2 |
Available as a free choice unit? | No |
Overview
Brief description of the unit:
Analysing and optimising the performance of application software often requires a detailed knowledge of the hardware architecture and low-level programming of computer systems, as well as the relevant analysis and synthesis skills. This unit provides students with these skills and knowledge. The unit is structured around the eight principal topics listed below.
- Fundamentals of computer architecture
- Processor instruction formats
- Quantitative performance analysis
- Memory hierarchy
- CISC and RISC architectures
- Arithmetic and data representation
- Instruction pipelining
- Multiprocessor architectures
Pre/co-requisites
Unit title | Unit code | Requirement type | Description |
---|---|---|---|
Microcontroller Engineering I | EEEN10202 | Pre-Requisite | Compulsory |
Digital System Design I | EEEN10131 | Pre-Requisite | Compulsory |
Microcontroller Engineering II | EEEN20011 | Pre-Requisite | Compulsory |
Digital Systems Design II | EEEN20121 | Pre-Requisite | Compulsory |
C Programming | EEEN10242 | Pre-Requisite | Compulsory |
Aims
The unit aims to:
Analysing and optimising the performance of software applications often requires a detailed knowledge of the hardware architecture and low-level programming of computer systems, as well as the relevant analysis and synthesis skills. This unit provides students with these skills and knowledge.
Learning outcomes
On the successful completion of the course, students will be able to:
ILO 1 - Describe in detail the operation of hardware architectural components and interpret specification information.
ILO 2 - Apply standard design techniques to specify or parameterise hardware architectural components
ILO 3 - Analyse the operation of hardware architectural components when executing programs
ILO 4 - Evaluate the performance of assembly language instruction sequences and synthesise optimised versions
ILO 5 - Create software to simulate the operation of hardware architectural components and derive performance metrics
Syllabus
The unit is structured around the eight principal topics listed below.
Fundamentals of computer architecture
Processor instruction formats
Quantitative performance analysis
Memory hierarchy
CISC and RISC architectures
Arithmetic and data representation
Instruction pipelining
Multiprocessor architectures
Teaching and learning methods
The unit is delivered through: 18 lectures, 6 Examples Classes and 2 Laboratory Classes. The Laboratory Classes are designed to reinforce key concepts from the lecture material.
Assessment methods
Method | Weight |
---|---|
Other | 20% |
Written exam | 80% |
Coursework:
2 laboratories both assessed in lab and 1 report to be submitted via Blackboard.
Coursework forms 20% of the unit assessment
Feedback methods
.
Recommended reading
J.L. Hennessy and D.A. Patterson, “Computer Organization and Design: The Hardware/Software Interface”, ARM Edition, Morgan Kaufmann, 2016.
J.L. Hennessy and D.A. Patterson, “Computer Architecture: A Quantitative Approach”, Sixth Edition, Morgan Kaufmann, 2017.
N. Nisan and S. Schocken, “The elements of computing systems : building a modern computer from first principles”, MIT Press, 2008.
S. William, "Computer Organization and Architecture : Designing for Performance", Eighth Edition, Boston, [Mass.] ; Pearson, 2010.
Study hours
Scheduled activity hours | |
---|---|
Lectures | 18 |
Practical classes & workshops | 6 |
Tutorials | 6 |
Independent study hours | |
---|---|
Independent study | 70 |
Teaching staff
Staff member | Role |
---|---|
Peter Green | Unit coordinator |