- UCAS course code
- G405
- UCAS institution code
- M20
Bachelor of Science (BSc)
BSc Computer Science with Industrial Experience
Duration: 4 years
Year of entry: 2025
UCAS course code: G405 / Institution code: M20
- Key features:
Industrial experience
Scholarships available
Accredited course
- Typical A-level offer: A*A*A including specific subjects
- Typical contextual A-level offer: AAA including specific subjects
- Refugee/care-experienced offer: AAB including specific subjects
- Typical International Baccalaureate offer: 38 points overall with 7,7,6 at HL, including specific requirements
Fees and funding
Fees
Tuition fees for home students commencing their studies in September 2025 will be £9,535 per annum (subject to Parliamentary approval). Tuition fees for international students will be £36,000 per annum. For general information please see the undergraduate finance pages.
Policy on additional costs
All students should normally be able to complete their programme of study without incurring additional study costs over and above the tuition fee for that programme. Any unavoidable additional compulsory costs totalling more than 1% of the annual home undergraduate fee per annum, regardless of whether the programme in question is undergraduate or postgraduate taught, will be made clear to you at the point of application. Further information can be found in the University's Policy on additional costs incurred by students on undergraduate and postgraduate taught programmes (PDF document, 91KB).
Scholarships/sponsorships
The University of Manchester is committed to attracting and supporting the very best students. We have a focus on nurturing talent and ability and we want to make sure that you have the opportunity to study here, regardless of your financial circumstances.
For information about scholarships and bursaries please visit our undergraduate student finance pages .
Course unit details:
Chip Multiprocessors
| Unit code | COMP35112 |
|---|---|
| Credit rating | 10 |
| Unit level | Level 3 |
| Teaching period(s) | Semester 2 |
| Available as a free choice unit? | Yes |
Overview
Due to technological limitations, it is proving increasingly difficult to maintain a continual increase in the performance of individual processors. Therefore, the current trend is to integrate multiple processors on to a single chip and exploit the resulting parallel resources to achieve higher computing power. However, this may require significantly different approaches to both hardware and software particularly for general purpose applications. This course will explore these issues in detail.
Pre/co-requisites
| Unit title | Unit code | Requirement type | Description |
|---|---|---|---|
| System Architecture | COMP25212 | Pre-Requisite | Compulsory |
Aims
The unit aims to:
Explore the various software and hardware issues brought by the current trends of integrating multiple processors on to a single chip in order to tackle the single-core processors speed stagnation through parallelism.
Learning outcomes
Describe the main issues, along with key proposed solutions, in the design and construction of chip multi-processor hardware (e.g. multi-core CPUs and GPUs) and related programming languages.
evaluate a number of specific examples of extensions to programming languages supporting the writing of correct and efficient code on shared memory multi-processors.
compare a number of extensions to hardware structures supporting, for example, memory coherence, synchronization, speculation and transactional memory, to improve the performance of code executing on chip multiprocessors.
Compare a number of extensions to programming languages and supporting user- and operating system-level data structures to improve the performance of code on chip multiprocessors.
evaluate the effectiveness of concurrency support in a popular programming language, including the use of threads, locks and barriers, in the context of experience gained with three simple parallel programming exercises.
Syllabus
Introduction
Trends in technology, limitations and consequences. The move to multi-coreParallelism in programs, ILP, Thread Level, Data Parallelism.
Parallel Architectures
SIMD, MIMD, Shared Memory, Distributed Memory, strengths and weaknesses.
Parallel Programming
Multithreaded programming, Data parallel programming, Explicit vs Implicit parallelism, automatic parallelisation. The Case for Shared Memory. When to share?
Shared Memory Multiprocessors
Basic structures, the cache coherence problem. The MESI protocol. Limitations. Directory based coherence.
Programming with Locks and Barriers
The need for synchronisation. Problems with explicit synchronisation
Other Parallel Programming Approaches
MPI and OpenMP
Speculation
The easy route to automatic parallelisation?
Transactional Memory
Principles. Hardware and Software approaches
Memory Issues
Memory system design. Memory consistency
Other Architectures and Programming Approaches
GPGPUs, CUDA
Data Driven Parallelism
Dataflow principles and Functional Programing
Employability skills
- Analytical skills
- Problem solving
- Written communication
- Other
Assessment methods
| Method | Weight |
|---|---|
| Written exam | 70% |
| Written assignment (inc essay) | 30% |
Feedback methods
Written feedback on reports for laboratory exercises. Students who attempt previous exam questions can get feedback on their answers.
Recommended reading
COMP35112 reading list can be found on the Department of Computer Science website for current students.
Study hours
| Scheduled activity hours | |
|---|---|
| Lectures | 24 |
| Independent study hours | |
|---|---|
| Independent study | 76 |
Teaching staff
| Staff member | Role |
|---|---|
| Pavlos Petoumenos | Unit coordinator |
| Pierre Olivier | Unit coordinator |
Additional notes
Course unit materials
Links to course unit teaching materials can be found on the School of Computer Science website for current students.