Bachelor of Engineering (BEng)

BEng Electrical and Electronic Engineering

*This course is now closed for applications for 2025 entry.

  • Duration: 3 years
  • Year of entry: 2025
  • UCAS course code: H600 / Institution code: M20
  • Key features:
  • Scholarships available
  • Accredited course

Full entry requirementsHow to apply

Course unit details:
Digital Systems Design II

Course unit fact file
Unit code EEEN20121
Credit rating 10
Unit level Level 2
Teaching period(s) Semester 1
Available as a free choice unit? No

Overview

This unit will cover the following:

  • Digital system design process. EDA tools and design viewpoints. Behavioural, dataflow, and gate-level descriptions.
  • Hardware description languages. VHDL modelling concepts. Behavioural and structural architecture descriptions. Concurrent and sequential statements. Event-driven simulation.
  • Building blocks for digital systems: tri-state buffers, multiplexers, latches, flip-flops, registers, counters, arithmetic circuits, finite state machines.
  • Design methodology. Synchronous systems. Top down design. Register-transfer-level design. Test benches. Synthesis from VHDL.
  • Implementation issues: gate delays, timing, critical path, communication between unsynchronised machines, coping with metastability.
  • Introduction to Programmable Logic Devices (FPGAs, CPLDs)

Pre/co-requisites

Unit title Unit code Requirement type Description
Digital System Design I EEEN10131 Pre-Requisite Compulsory

Aims

This course unit aims to: Enable students to use structured digital system design methods, hardware description languages and verification tools to design digital systems. Expose students to practical implementation issues for digital systems.

Learning outcomes

On the successful completion of the course, students will be able to:

ILO 1 - Predict behavior of a component specified using a Hardware Description Language (VHDL). [Developed] [Assessed]

ILO 2 - Produce VHDL descriptions of digital data-path components, finite state machines and algorithmic state machines. [Developed] [Assessed]

ILO 3 - Design and implement simple synchronous digital systems using FPGA hardware. [Developed] [Assessed]

ILO 4 - Estimate timing performance limits of a given digital circuit. [Developed] [Assessed]

Teaching and learning methods

 

Assessment methods

Method Weight
Other 20%
Written exam 80%

Coursework:

Course work forms 20% of the unit assessment and is both formative and summative. Completion of all coursework is mandatory.

Feedback methods

.

Recommended reading

Digital design : with an introduction to the Verilog HDL, VHDL, and SystemVerilog: Mano, M. Morris, Pearson Education Limited, 2019. ISBN: 9781292231181
The student's guide to VHDL: Ashenden, Peter J., Morgan Kaufmann/Elsevier, 2008. ISBN: 0080948553
The designer's guide to VHDL: Ashenden, Peter J., Morgan Kaufmann Publishers, 2008. ISBN: 9780120887859
VHDL made easy!: Pellerin, David., Prentice Hall, 1997. ISBN: 0136507638
Digital system design with VHDL: Zwoliński, Mark, Prentice Hall, 2004. 

Study hours

Scheduled activity hours
Lectures 11
Practical classes & workshops 9
Independent study hours
Independent study 80

Teaching staff

Staff member Role
Piotr Dudek Unit coordinator

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